We have clarified our Privacy Statement even further. Please have a look at our changes.
Parser for Verilog netlists (structural Verilog).
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
Thomas Kramer e15ad7414d Introduce class for concatenations. 1 week ago
test_data Output a list of Modules in all cases. 2 weeks ago
verilog_parser Introduce class for concatenations. 1 week ago
.gitignore Initial commit. 7 months ago
LICENSE :scroll: License file. 7 months ago
README.md Update README. 2 months ago
setup.py Initial commit. 7 months ago

README.md

Verilog parser for Python

Lark based parser for Verilog netlists (structural Verilog without behavioral statements). This is meant to be used to read netlists as generated by HDL logic synthesizers such as Yosys.

Example

from verilog_parser.parser import parse_verilog
ast = parse_verilog(open(verilog_file_path).read())