Parser for Verilog netlists (structural Verilog).
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Thomas Kramer dd03c45d90 Ignore *.pyc. 6 months ago
test_data Output a list of Modules in all cases. 7 months ago
verilog_parser Introduce class for concatenations. 6 months ago
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LICENSE :scroll: License file. 1 year ago Update README. 8 months ago Initial commit. 1 year ago

Verilog parser for Python

Lark based parser for Verilog netlists (structural Verilog without behavioral statements). This is meant to be used to read netlists as generated by HDL logic synthesizers such as Yosys.


from verilog_parser.parser import parse_verilog
ast = parse_verilog(open(verilog_file_path).read())