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4 days ago | |
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examples | 3 weeks ago | |
lclayout | 3 weeks ago | |
.gitignore | 2 years ago | |
LICENCE | 9 months ago | |
LICENSE | 2 years ago | |
README.md | 2 years ago | |
setup.py | 4 days ago |
CMOS Standard Cell layout generator.
See install instructions in top-project.
Generate a layout from a SPICE netlist which includes the transistor sizes:
.subckt
).mkdir mylibrary
lclayout --output-dir mylibrary --tech examples/dummy_tech.py --netlist examples/cells.sp --cell AND2X1
Design rulesi and technology related data need to be encoded in a Python script file as shown in examples/dummy_tech.py
.