tok
/
librecell
Watch 1
Star 0
Fork 1
Code Issues 2 Pull Requests 0 Releases 0 Wiki Activity
CMOS standard cell generator and characterization suite.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
159 Commits
2 Branches
1.5MB
Branch: master
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from 'master'
${ noResults }
librecell/librecell-layout
Thomas Kramer ba60255248 signal_router: Remove unused import. 9 hours ago
..
examples Examples: also output metal2 layer to Magic. 1 week ago
lclayout signal_router: Remove unused import. 9 hours ago
.gitignore Start splitting projects. 11 months ago
LICENSE :scroll: Change license to OHL-S v2.0. 11 months ago
README.md Fix formatting bug. 11 months ago
setup.py setup.py: add toml. 1 week ago

README.md

LibreCell - Layout

CMOS Standard Cell layout generator.

Getting started

See install instructions in top-project.

Generate a layout

Generate a layout from a SPICE netlist which includes the transistor sizes:

  • --output-dir: Directory which will be used to store GDS and LEF of the cell
  • --tech: Python script file containing design rules and technology related data
  • --netlist: A SPICE netlist containing the netlist of the cell as a sub circuit (.subckt).
  • --cell: Name of the cell. Must match the name of the sub circuit in the SPICE netlist.
mkdir mylibrary
lclayout --output-dir mylibrary --tech examples/dummy_tech.py --netlist examples/cells.sp --cell AND2X1

Adapting design rules

Design rulesi and technology related data need to be encoded in a Python script file as shown in examples/dummy_tech.py.