CMOS standard-cell generator and characterization suite.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
Thomas Kramer 1607667951 More flexibility for dependencies. 4 days ago
..
examples Fixes for separated ndiff/pdiff contacts. 3 weeks ago
lclayout SMT placer: Fix incomplete renaming of source and drain attribute names. 3 weeks ago
.gitignore Start splitting projects. 2 years ago
LICENCE 📜 Include CERN OHL-S v2. 9 months ago
LICENSE 📜 Change license to OHL-S v2.0. 2 years ago
README.md Fix formatting bug. 2 years ago
setup.py More flexibility for dependencies. 4 days ago

README.md

LibreCell - Layout

CMOS Standard Cell layout generator.

Getting started

See install instructions in top-project.

Generate a layout

Generate a layout from a SPICE netlist which includes the transistor sizes:

  • --output-dir: Directory which will be used to store GDS and LEF of the cell
  • --tech: Python script file containing design rules and technology related data
  • --netlist: A SPICE netlist containing the netlist of the cell as a sub circuit (.subckt).
  • --cell: Name of the cell. Must match the name of the sub circuit in the SPICE netlist.
mkdir mylibrary
lclayout --output-dir mylibrary --tech examples/dummy_tech.py --netlist examples/cells.sp --cell AND2X1

Adapting design rules

Design rulesi and technology related data need to be encoded in a Python script file as shown in examples/dummy_tech.py.