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librecell
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Timing characterization
Recognition of sequential cells
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tok
  • Routing Usage
    #31 opened 2 months ago by Sourcerer
    6
  • Routing Failure debugging
    #30 opened 2 months ago by Sourcerer
  • Retry with a different placer if one is unsuccessful
    #29 opened 2 months ago by Sourcerer
    3
  • Failed to route well-taps. No via layer is specified that connects to layer 'pdiff_contact'..
    #26 opened 8 months ago by lokesh
  • LVS Issue
    #23 opened 1 year ago by Sourcerer
    1
  • Multi-Layer Power-Rail
    #22 opened 1 year ago by Sourcerer
  • Support for transistors that are wrapped into circuits. bug
    #20 opened 2 years ago by tok
  • y-offset of Routing grid.
    #19 opened 2 years ago by tok
  • Adding well-taps
    #18 opened 2 years ago by Sourcerer
    3
  • Remove pyo3_graphrouter dependencies.
    #15 opened 2 years ago by tok
  • Add possiblity for pre/post-processing of the layout. enhancement
    #12 opened 2 years ago by tok
    1
  • Layers for Sky130 (NPC, diff, tap, pdsm, ndsm) question
    #11 opened 2 years ago by tok
    3
  • Liberty: power & ground pins enhancement
    #10 opened 2 years ago by tok
  • LEF output: Need enhancements and corrections in the file format. bug
    #8 opened 2 years ago by tok
    3
  • EulerPlacer: Handle cells with transmission gates efficiently. enhancement
    #1 opened 4 years ago by tok master