LibrEDA

libreda-lefdef

Rust 1 1

LEF/DEF input and output module for LibrEDA.

rust vlsi parser def lef lefdef

Updated 2024-09-26 16:06:36 +00:00

libreda-db

Rust 3 2

Layout and netlist data structures for the Rust LibrEDA framework.

rust vlsi libreda database netlist db layout

Updated 2024-09-26 15:32:32 +00:00

libreda-logic

Rust 0 0

Core traits and data types for representation and manipulation of logic functions.

rust eda logic boolean mig aig networks

Updated 2024-09-19 21:03:35 +00:00

iron-shapes-booleanop

Rust 0 1

Boolean operations on polygons for the `iron-shapes` crate.

rust vlsi geometry polygon boolean martinez operation euclidean

Updated 2024-09-18 07:52:45 +00:00

libreda-core

Rust 0 0

Core traits for EDA applications.

eda

Updated 2024-09-16 19:39:29 +00:00

libreda-rs-workspace

Rust 0 0

Repository holding the cargo workspace of LibrEDA with all sub-projects. This is meant as a way to distribute the most recent source-code.

rust vlsi libreda hardware framework workspace silicon route place

Updated 2024-09-14 09:33:36 +00:00

libreda-regionsearch

Rust 0 0

Fast region search using r-trees for chip layouts.

Updated 2024-09-14 09:25:18 +00:00

splay

Rust 0 1

Splay map and splay set data structures.

rust splay-tree splay-map splay-set

Updated 2024-09-10 10:02:01 +00:00

libreda-structural-verilog

Rust 0 2

Verilog netlist parser and writer for LibrEDA. Only supports the structural Verilog syntax as used by Yosys.

rust vlsi parser libreda io netlist yosys verilog

Updated 2024-09-10 10:01:58 +00:00

libreda-sta

Rust 0 0

Static timing analysis (STA) for netlists of the LibrEDA framework.

rust vlsi libreda analysis sta timing

Updated 2024-09-10 10:01:56 +00:00

libreda-pnr

Rust 1 1

ASIC place & route framework. This crate contains interface definitions of the core parts of the place & route flow.

rust vlsi place-and-route

Updated 2024-09-10 10:01:53 +00:00

libreda-oasis

Rust 0 1

Layout writer and reader for the OASIS stream format.

rust vlsi io oasis

Updated 2024-09-10 10:01:52 +00:00

libreda-examples

Coq 0 1

A minimal place & route flow build on top of the LibrEDA framework and the FreePDK45. This is work-in-progress but already good enough for a demonstration.

rust vlsi libreda electronics hardware example chip silicon place flow route open-hardware

Updated 2024-09-10 10:01:47 +00:00

liberty-io

Rust 0 0

Rust crate of a parser and writer for the 'liberty' format which is used to describe the timing behavior of CMOS standard-cells.

vlsi libreda parser eda liberty

Updated 2024-09-10 10:01:42 +00:00

iron-shapes

Rust 3 3

Primitive data types and basic routines for Euclidean geometry in the plane. This is developed as a core geometry library of LibrEDA.

rust vlsi libreda geometry

Updated 2024-09-10 10:01:37 +00:00

Members 1