LibrEDA

The LibrEDA project is focused on creating a libre-software framework for the physical design of silicon chips.

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Example router implementation for the LibrEDA framework.

Updated 2 days ago

Design rule checks for the LibrEDA framework.

Updated 2 days ago

Primitive data types and basic routines for Euclidean geometry in the plane. This is developed as a core geometry library of LibrEDA.

Updated 4 days ago

Layout and netlist data structures for the Rust LibrEDA framework.

Updated 1 week ago

Rust and LibrEDA bindings for the TritonRoute detail router.

Updated 2 weeks ago

LEF/DEF input and output module for LibrEDA.

Updated 2 weeks ago

A minimal place & route flow build on top of the LibrEDA framework and the FreePDK45. This is work-in-progress but already good enough for a demonstration.

Updated 2 weeks ago

Example standard-cell placement engine for the LibrEDA-Rust framework. This placement algorithm simulates the movement of electric charges that are sparsely connected by springs (wires).

Updated 3 weeks ago

Verilog netlist parser and writer for LibrEDA. Only supports the structural Verilog syntax as used by Yosys.

Updated 3 weeks ago

Layout writer and reader for the OASIS stream format.

Updated 3 weeks ago

Boolean operations on polygons for the `iron-shapes` crate.

Updated 4 weeks ago

Standard-cell legalizer example implementations for the LibrEDA place&route framework.

Updated 4 weeks ago

Fast lookup-table based computation of rectilinear Steiner minimal trees (RSMT).

Updated 1 month ago

Geometric algorithms for the iron-shapes geometry library.

Updated 2 months ago

LibrEDA project web page.

Updated 2 months ago

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