The LibrEDA project is focused on creating a libre-software framework for the physical design of silicon chips.
LibrEDA project web page.
Updated 4 weeks ago
Repository holding the cargo workspace of LibrEDA with all sub-projects. This is meant as a way to distribute the most recent source-code.
Updated 1 month ago
Example clock-tree generator for the LibrEDA framework
Updated 1 month ago
Layout and netlist data structures for the Rust LibrEDA framework.
Updated 1 month ago
Static timing analysis (STA) for netlists of the LibrEDA framework.
Updated 1 month ago
Rust crate of a parser and writer for the 'liberty' format which is used to describe the timing behavior of CMOS standard-cells.
Updated 1 month ago
Standard-cell legalizer example implementations for the LibrEDA place&route framework.
Updated 1 month ago
Example router implementation for the LibrEDA framework.
Updated 1 month ago
LEF/DEF input and output module for LibrEDA.
Updated 2 months ago
A minimal place & route flow build on top of the LibrEDA framework and the FreePDK45. This is work-in-progress but already good enough for a demonstration.
Updated 2 months ago
The ultimate guide through LibrEDA.
Updated 2 months ago
Example standard-cell placement engine for the LibrEDA-Rust framework. This placement algorithm simulates the movement of electric charges that are sparsely connected by springs (wires).
Updated 2 months ago
Libre EDA Project. LibrEDA aims to create a libre software framework for the physical design of silicon chips. This repository is a project management repository. It is used to keep track of general milestones etc.
Updated 2 months ago
ASIC place & route framework. This crate contains interface definitions of the core parts of the place & route flow.
Updated 2 months ago
Verilog netlist parser and writer for LibrEDA. Only supports the structural Verilog syntax as used by Yosys.
Updated 2 months ago
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