The LibrEDA project is focused on creating a libre-software framework for the physical design of silicon chips.
Example clock-tree generator for the LibrEDA framework
Updated 3 days ago
Rust crate of a parser and writer for the 'liberty' format which is used to describe the timing behavior of CMOS standard-cells.
Updated 3 days ago
LibrEDA project web page.
Updated 3 days ago
Example router implementation for the LibrEDA framework.
Updated 4 days ago
Primitive data types and basic routines for Euclidean geometry in the plane. This is developed as a core geometry library of LibrEDA.
Updated 6 days ago
LEF/DEF input and output module for LibrEDA.
Updated 1 week ago
ASIC place & route framework. This crate contains interface definitions of the core parts of the place & route flow.
Updated 1 week ago
Layout writer and reader for the OASIS stream format.
Updated 1 week ago
Layout and netlist data structures for the Rust LibrEDA framework.
Updated 1 week ago
Boolean operations on polygons for the `iron-shapes` crate.
Updated 1 week ago
Standard-cell legalizer example implementations for the LibrEDA place&route framework.
Updated 1 month ago
Splay map and splay set data structures.
Updated 1 month ago
Verilog netlist parser and writer for LibrEDA. Only supports the structural Verilog syntax as used by Yosys.
Updated 1 month ago
Netlist reader and writer implementations for the JSON format used by Yosys.
Updated 1 month ago
Libre EDA Project. LibrEDA aims to create a libre software framework for the physical design of silicon chips. This repository is a project management repository. It is used to keep track of general milestones etc.
Updated 2 months ago