123 lines
4.2 KiB
Forth
123 lines
4.2 KiB
Forth
\ **********************************************************************
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\
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\ ad9833.fs is part of the ff-ad9833 project
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\ ff-ad9833 is an audio project for FlashForth and the AD9833
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\ Copyright (C) 2021 Christopher Howard
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\ SPDX-License-Identifier: GPL-3.0-or-later
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\ This program is free software: you can redistribute it and/or modify
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\ it under the terms of the GNU General Public License as published by
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\ the Free Software Foundation, either version 3 of the License, or
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\ (at your option) any later version.
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\ This program is distributed in the hope that it will be useful,
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\ but WITHOUT ANY WARRANTY; without even the implied warranty of
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\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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\ GNU General Public License for more details.
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\ You should have received a copy of the GNU General Public License
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\ along with this program. If not, see <https://www.gnu.org/licenses/>.
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\ The purpose of this file is to provide basic words for setting up
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\ communication with the ad9833 chip, and for sending data to the ad9833
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\ registers.
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\ The code assumes by default that fsync line is PD4 (Arduino DP4) but
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\ this can be adjust be altering the fsync-ddr, fsync-port, and
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\ fsync-bit constants.
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\
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\ Public words:
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\ FREG0_PF FREG1_PF PHREG0_PF PHREG1_PF B28_BT HLB_BT FSELECT_BT
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\ PSELECT_BT RESET_BT SLEEP1_BT SLEEP12_BT OPBITEN_BT DIV2_BT MODE_BT
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\ fsync-ddr fsync-port fsync-bit init-spi init-fsync fsync-low
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\ fsync-high demo-1000hz
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\ **********************************************************************
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ad9833
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marker ad9833
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\ **********************************************************************
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\ Register prefixes and bit definition constants for the ad9833.
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\ These correspond to their equivalent values in the ad9833 data sheet.
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\ The control register has bit prefix 00 so we do not waste memory
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\ defining it.
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\ **********************************************************************
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%0100000000000000 constant FREG0_PF
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%1000000000000000 constant FREG1_PF
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%1100000000000000 constant PHREG0_PF
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%1110000000000000 constant PHREG1_PF
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#13 constant B28_BT
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#12 constant HLB_BT
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#11 constant FSELECT_BT
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#10 constant PSELECT_BT
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#08 constant RESET_BT
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#07 constant SLEEP1_BT
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#06 constant SLEEP12_BT
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#05 constant OPBITEN_BT
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#03 constant DIV2_BT
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#01 constant MODE_BT
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\ **********************************************************************
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\ Parameter constants for the fsync line, in case you need to adjust
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\ which pin is the fsync line.
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\ **********************************************************************
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DDRD constant fsync-ddr
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PORTD constant fsync-port
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#4 constant fsync-bit
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\ **********************************************************************
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\ Words for setting up communications with the ad9833
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\ **********************************************************************
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: init-spi ( -- )
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DD_OUT DD_MOSI lshift
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DD_OUT DD_SCK lshift or
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DD_OUT DD_SS lshift or DDR_SPI mset
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1 SPR0 lshift
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0 SPR1 lshift or
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CPHA_SMPLED CPHA lshift or
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CPOL_HIDLE CPOL lshift or
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MSTR_MSTR MSTR lshift or
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DORD_MSB DORD lshift or
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SPE_ENAB SPE lshift or
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SPIE_DISAB SPIE lshift or SPCR c!
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;
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: init-fsync ( -- ) [ 1 fsync-bit lshift ] literal fsync-ddr mset ;
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: fsync-low ( -- ) [ 1 fsync-bit lshift ] literal fsync-port mclr ;
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: fsync-high ( -- ) [ 1 fsync-bit lshift ] literal fsync-port mset ;
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\ **********************************************************************
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\ The demo steps are as follows:
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\ 1. initialize spi communication
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\ 2. set fsync pin to output
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\ 3. bring fsync line low
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\ 4. Enter chip reset state & prep to load frequency register
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\ 5. set phase register to 0
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\ 6. load lower 16 bits into frequency register 0
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\ 7. load higher 16 bits into frequency register 0
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\ 8. exit reset status (initiates output)
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\ 9. wait two seconds and then enable chip reset, to silence output
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\ 10. bring fysnc line back up to high
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\ **********************************************************************
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: demo-1000hz ( -- )
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init-spi
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init-fsync
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fsync-low
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[ 1 B28_BT lshift ] literal [ 1 RESET_BT lshift ] literal or 2tx-spi
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PHREG0_PF 2tx-spi
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[ FREG0_PF $29f1 or ] literal 2tx-spi
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FREG0_PF 2tx-spi
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0 2tx-spi
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#2000 ms [ 1 RESET_BT lshift ] literal 2tx-spi
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fsync-high
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;
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