LOLcpu - my try to implement GRU ocpu https://g1n.ttm.sh/lolcpu/
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<h1>LOLcpu - my try to implement <a href="https://g1n.ttm.sh/gru/ocpu">GRU ocpu</a></h1>
<p>This is going to be something like log, where I am sharing some thoughts about electronics or circuits what I have done</p>
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<h2>Some thoughts about first big cpu goal</h2>
<p>I think it will be unreal to implement ocpu specs in tiny amount of time, it may take ages.</p>
<p>So i decided to start from something easier.</p>
<p>My idea is to make cpu that have program counter, instruction register, and one general purpose register.</p>
<p>It will have 4 instructions - CLR, INC, DEC, FLR. CLR is instruction to set all zeros to general register.</p>
<p>INC and DEC is incrementing and decrementing its value. And FLR is too set maximum of that register (all ones).</p>
<p>I think that register should be at least 2-bit (but 4-bit mostly recommended), to know that it is working :)</p>
<p align="right"><b>24-10-2021</b></p>
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<h2>Some logic gates</h2>
<p>I have bought about 60 transistors maybe even less and some other electoronic parts.</p>
<p>Currently I have done OR, NOT, AND, NAND, and NOR gates</p>
<p>AND was the hardest, because I didn't undertand that resistors are required :). But now I understood my mistake.</p>
<p>Now the hardest is XOR, because I not really understand it and have a lot of mistakes when trying to make it.</p>
<p align="right"><b>24-10-2021</b></p>
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<h2>Half-adder circuit without XOR</h2>
<img src="https://ttm.sh/enP.png" width="874px">
<p align="right"><b>25-10-2021</b></p>
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