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====== Introduction to Verilog and ModelSim ======
//**This page is intended for the participants of 'Introduction to Verilog and ModelSim' training course (July 19-21, 2016).**//
//**Updated20160718: The course has been postponed to August 1-3, 2016.**//
Many electronic system design work involves Hardware Description Language (HDL) coding. Verilog HDL is one of the easiest HDL to learn and is the preferred language especially for entry-level engineers. This is because of its simplicity (e.g. as opposed to VHDL which is strongly typed) and its C-like syntax (which most engineering students would be familiar with). ModelSim is an industry-standard HDL simulation environment by Mentor Graphics® that is used (among others) for Integrated Circuit (IC) design, FPGA-based digital designs, or simply for logic verification.
====== Course Objectives ======
This course is designed to provide introductory-level practical knowledge on using Verilog and ModelSim for simple digital logic/system design.
====== Learning Outcomes ======
Upon completion of this course, the participants should be able to:
- Understand the basic requirements in implementing digital design using HDL
- Create and implement a simple digital logic design using Verilog
- Test and verify a simple digital logic design using ModelSim
====== Who Will Benefit From This Course ======
This course is designed for engineers, researchers, system designers, technical specialists, graduate students and individuals who are interested in developing fundamental skills on digital systems development, especially on FPGA platform.
//Related keywords: HDL, Verilog, ModelSim, Digital Logic/Systems Design.//
====== Course Content ======
^ Sessions ^ Details ^ Materials ^ Notes ^
^ Session 1 | <WRAP>
* Introduction to Verilog
* Overall view on CAD-based design flow
* Introduction to HDLs
* Introduction to Digital Simulation Tool
* Implementing simple logic design using Verilog
* Implementing simple testbench using Verilog
</WRAP> | <WRAP>
{{:archive:pgt206:verilog_p1.pdf|Slide 1}}
{{:archive:pgt206:verilog_p2.pdf|Slide 2}}
</WRAP> | <WRAP>
Mainly a theoretical session
</WRAP> |
^ Session 2 | <WRAP>
* Using ModelSim
* Creating a new project on ModelSim
* Add/create Verilog files to the project
* Run simulation using ModelSim
* Analyze waveform based on simulation results
</WRAP> | <WRAP>
{{:archive:pgt206:verilog_p3.pdf|Slide 3}}
</WRAP> | <WRAP>
Step-by-step software session
</WRAP> |
^ Session 3 & 4 | <WRAP>
* Combinational Logic
* Moving towards designing an ALU
</WRAP> | <WRAP>
{{:archive:pgt206:verilog_p4.pdf|Slide 4}}
</WRAP> | <WRAP>
A more practical session (2 slots)
</WRAP> |
^ Session 5 & 6 | <WRAP>
* Sequential Logic
* Moving towards designing a register block
(This is optional and depends on participants' progress)
* State Machines and Control Logic
* Moving towards designing control block
</WRAP> | <WRAP>
{{:archive:pgt206:verilog_p5.pdf|Slide 5}}
{{:archive:pgt206:verilog_p6.pdf|Slide 6 (Optional)}}
</WRAP> | <WRAP>
A more practical session (2 slots)
</WRAP> |