Verilog netlist parser and writer for LibrEDA. Only supports the structural Verilog syntax as used by Yosys.
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Thomas Kramer 33d9c35177 Adapt to changes in netlist traits. 1 week ago
src Adapt to changes in netlist traits. 1 week ago
tests Clean for publication. 5 months ago
.gitignore Ignore verilog test output. 5 months ago
Cargo.toml Allow incomplete port connections for named ports. 5 months ago
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README.md Clean for publication. 5 months ago
build.rs Clean for publication. 5 months ago

README.md

Verilog Netlist I/O for LibrEDA

This crate implements a NetlistReader and NetlistWriter of the LibrEDA framework for the Verilog netlist format used by Yosys.

Only a subset of Verilog is supported, namely 'structural' or 'netlist' Verilog. Which consists only of modules, module instantiations and port connections.