A minimal place & route flow build on top of the LibrEDA framework and the FreePDK45. This is work-in-progress but already good enough for a demonstration. https://libreda.org
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# Run a simple-stupid example place and route flow.
# Inputs are: Directory to the cell layouts, a verilog file with the cell interfaces
# a LEF file with the cell library, a synthesized gate-level netlist the name of the top-level cell
# and core dimensions.
# Use the --help argument to display documentation on the arguments.
RUST_LOG=info cargo run \
--bin libreda-example -- \
--cell-layouts test/data/oas/ \
--cell-library test/data/gscl45nm_interfaces.v \
--lef test/data/gscl45nm.lef \
--netlist test/data/comb_chip_45_nl.v \
--top my_chip \
--height 50000 --width 50000 \
--output test/example_output.oas