Simple framework for physical chip design (place & route) based on KLayout.
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/* Generated by Yosys 0.9+932 (git sha1 81876a37, clang 7.0.1-8 -fPIC -Os) */
(* cells_not_processed = 1 *)
(* src = "seq_chip/seq_chip_simple.v:1" *)
module seq_chip(clk_i, rst_ni, data_i, data_o);
(* src = "seq_chip/seq_chip_simple.v:2" *)
wire _0_;
(* src = "seq_chip/seq_chip_simple.v:6" *)
wire _1_;
(* src = "seq_chip/seq_chip_simple.v:8" *)
wire _2_;
(* src = "seq_chip/seq_chip_simple.v:2" *)
input clk_i;
(* src = "seq_chip/seq_chip_simple.v:18" *)
wire data_0_i;
(* src = "seq_chip/seq_chip_simple.v:2" *)
input data_i;
(* src = "seq_chip/seq_chip_simple.v:3" *)
output data_o;
(* src = "seq_chip/seq_chip_simple.v:6" *)
(* unused_bits = "1" *)
wire [1:0] inp_reg_q;
(* src = "seq_chip/seq_chip_simple.v:8" *)
(* unused_bits = "1" *)
wire [1:0] oup_reg_d;
(* src = "seq_chip/seq_chip_simple.v:7" *)
(* unused_bits = "1" *)
wire [1:0] oup_reg_q;
(* src = "seq_chip/seq_chip_simple.v:2" *)
input rst_ni;
AND2X1 _3_ (
.A(_1_),
.B(_0_),
.Y(_2_)
);
(* src = "seq_chip/seq_chip_simple.v:13" *)
DFFSR _4_ (
.CLK(clk_i),
.D(data_0_i),
.Q(inp_reg_q[0]),
.R(rst_ni),
.S(1'h1)
);
(* src = "seq_chip/seq_chip_simple.v:13" *)
DFFSR _5_ (
.CLK(clk_i),
.D(oup_reg_d[0]),
.Q(oup_reg_q[0]),
.R(rst_ni),
.S(1'h1)
);
assign data_o = oup_reg_q[0];
assign _1_ = inp_reg_q[0];
assign _0_ = data_i;
assign oup_reg_d[0] = _2_;
endmodule