Simple framework for physical chip design (place & route) based on KLayout.
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// This file was automatically generated by verilog_writer
module seq_chip (
clk_i_22,
data_0_i_23,
data_1_i_24,
data_2_i_25,
rst_ni_26,
data_0_o_27,
data_1_o_28,
);
input clk_i_22;
input data_0_i_23;
input data_1_i_24;
input data_2_i_25;
input rst_ni_26;
output data_0_o_27;
output data_1_o_28;
wire clk_i_22;
wire data_0_i_23;
wire data_1_i_24;
wire data_2_i_25;
wire rst_ni_26;
wire data_0_o_27;
wire data_1_o_28;
wire __HIGH__;
wire _03__5;
wire _04__6;
wire _05__7;
wire _06__8;
wire _07__9;
wire inp_reg_q_15;
wire inp_reg_q_16;
wire inp_reg_q_17;
NAND2X1 _13_(
.A( inp_reg_q_17 ),
.B( inp_reg_q_15 ),
.Y( _03__5 ),
);
XNOR2X1 _14_(
.A( inp_reg_q_17 ),
.B( inp_reg_q_15 ),
.Y( _04__6 ),
);
OAI21X1 _15_(
.A( inp_reg_q_17 ),
.B( inp_reg_q_15 ),
.C( inp_reg_q_16 ),
.Y( _05__7 ),
);
NAND2X1 _16_(
.A( _03__5 ),
.B( _05__7 ),
.Y( _07__9 ),
);
XNOR2X1 _17_(
.A( inp_reg_q_16 ),
.B( _04__6 ),
.Y( _06__8 ),
);
DFFSR _18_(
.CLK( clk_i_22 ),
.D( data_2_i_25 ),
.Q( inp_reg_q_17 ),
.R( rst_ni_26 ),
.S( __HIGH__ ),
);
DFFSR _19_(
.CLK( clk_i_22 ),
.D( data_1_i_24 ),
.Q( inp_reg_q_16 ),
.R( rst_ni_26 ),
.S( __HIGH__ ),
);
DFFSR _20_(
.CLK( clk_i_22 ),
.D( data_0_i_23 ),
.Q( inp_reg_q_15 ),
.R( rst_ni_26 ),
.S( __HIGH__ ),
);
DFFSR _21_(
.CLK( clk_i_22 ),
.D( _06__8 ),
.Q( data_1_o_28 ),
.R( rst_ni_26 ),
.S( __HIGH__ ),
);
DFFSR _22_(
.CLK( clk_i_22 ),
.D( _07__9 ),
.Q( data_0_o_27 ),
.R( rst_ni_26 ),
.S( __HIGH__ ),
);
endmodule : seq_chip