Simple framework for physical chip design (place & route) based on KLayout.
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/* Generated by Yosys 0.8+312 (git sha1 22035c20, clang 6.0.0-1ubuntu2 -fPIC -Os) */
(* cells_not_processed = 1 *)
(* src = "../seq_chip/seq_chip.v:1" *)
module seq_chip(clk_i, rst_ni, data_0_i, data_1_i, data_2_i, data_0_o, data_1_o);
(* src = "../seq_chip/seq_chip.v:6" *)
wire _00_;
(* src = "../seq_chip/seq_chip.v:6" *)
wire _01_;
(* src = "../seq_chip/seq_chip.v:6" *)
wire _02_;
wire _03_;
wire _04_;
wire _05_;
(* src = "../seq_chip/seq_chip.v:8" *)
wire _06_;
(* src = "../seq_chip/seq_chip.v:8" *)
wire _07_;
(* src = "../seq_chip/seq_chip.v:12" *)
wire _08_;
(* src = "../seq_chip/seq_chip.v:12" *)
wire _09_;
(* src = "../seq_chip/seq_chip.v:12" *)
wire _10_;
(* src = "../seq_chip/seq_chip.v:12" *)
wire _11_;
(* src = "../seq_chip/seq_chip.v:11" *)
wire _12_;
(* src = "../seq_chip/seq_chip.v:2" *)
input clk_i;
(* src = "../seq_chip/seq_chip.v:2" *)
input data_0_i;
(* src = "../seq_chip/seq_chip.v:3" *)
output data_0_o;
(* src = "../seq_chip/seq_chip.v:2" *)
input data_1_i;
(* src = "../seq_chip/seq_chip.v:3" *)
output data_1_o;
(* src = "../seq_chip/seq_chip.v:2" *)
input data_2_i;
(* src = "../seq_chip/seq_chip.v:6" *)
wire [2:0] inp_reg_q;
(* src = "../seq_chip/seq_chip.v:8" *)
wire [1:0] oup_reg_d;
(* src = "../seq_chip/seq_chip.v:7" *)
wire [1:0] oup_reg_q;
(* src = "../seq_chip/seq_chip.v:2" *)
input rst_ni;
NAND2X1 _13_ (
.A(_00_),
.B(_02_),
.Y(_03_)
);
XNOR2X1 _14_ (
.A(_00_),
.B(_02_),
.Y(_04_)
);
OAI21X1 _15_ (
.A(_00_),
.B(_02_),
.C(_01_),
.Y(_05_)
);
NAND2X1 _16_ (
.A(_03_),
.B(_05_),
.Y(_07_)
);
XNOR2X1 _17_ (
.A(_01_),
.B(_04_),
.Y(_06_)
);
(* src = "../seq_chip/seq_chip.v:15" *)
DFFSR _18_ (
.CLK(clk_i),
.D(data_2_i),
.Q(inp_reg_q[0]),
.R(rst_ni),
.S(1'h1)
);
(* src = "../seq_chip/seq_chip.v:15" *)
DFFSR _19_ (
.CLK(clk_i),
.D(data_1_i),
.Q(inp_reg_q[1]),
.R(rst_ni),
.S(1'h1)
);
(* src = "../seq_chip/seq_chip.v:15" *)
DFFSR _20_ (
.CLK(clk_i),
.D(data_0_i),
.Q(inp_reg_q[2]),
.R(rst_ni),
.S(1'h1)
);
(* src = "../seq_chip/seq_chip.v:15" *)
DFFSR _21_ (
.CLK(clk_i),
.D(oup_reg_d[0]),
.Q(oup_reg_q[0]),
.R(rst_ni),
.S(1'h1)
);
(* src = "../seq_chip/seq_chip.v:15" *)
DFFSR _22_ (
.CLK(clk_i),
.D(oup_reg_d[1]),
.Q(oup_reg_q[1]),
.R(rst_ni),
.S(1'h1)
);
assign data_0_o = oup_reg_q[1];
assign data_1_o = oup_reg_q[0];
assign _00_ = inp_reg_q[0];
assign _01_ = inp_reg_q[1];
assign _02_ = inp_reg_q[2];
assign oup_reg_d[0] = _06_;
assign oup_reg_d[1] = _07_;
endmodule