Simple framework for physical chip design (place & route) based on KLayout.
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/* Generated by Yosys 0.8+312 (git sha1 22035c20, clang 6.0.0-1ubuntu2 -fPIC -Os) */
(* cells_not_processed = 1 *)
(* src = "examples/my_chip.v:1" *)
module my_chip(a_op_0_pad, a_op_1_pad, a_op_2_pad, a_op_3_pad, a_op_4_pad, a_op_5_pad, b_op_0_pad, b_op_1_pad, b_op_2_pad, b_op_3_pad, b_op_4_pad, b_op_5_pad, add_0_pad, add_1_pad, add_2_pad, add_3_pad, add_4_pad, add_5_pad, sub_0_pad, sub_1_pad, sub_2_pad, sub_3_pad, sub_4_pad, sub_5_pad);
(* src = "examples/my_chip.v:5" *)
wire [5:0] a;
(* src = "examples/my_chip.v:2" *)
input a_op_0_pad;
(* src = "examples/my_chip.v:2" *)
input a_op_1_pad;
(* src = "examples/my_chip.v:2" *)
input a_op_2_pad;
(* src = "examples/my_chip.v:2" *)
input a_op_3_pad;
(* src = "examples/my_chip.v:2" *)
input a_op_4_pad;
(* src = "examples/my_chip.v:2" *)
input a_op_5_pad;
(* src = "examples/my_chip.v:5" *)
wire [5:0] add;
(* src = "examples/my_chip.v:3" *)
output add_0_pad;
(* src = "examples/my_chip.v:3" *)
output add_1_pad;
(* src = "examples/my_chip.v:3" *)
output add_2_pad;
(* src = "examples/my_chip.v:3" *)
output add_3_pad;
(* src = "examples/my_chip.v:3" *)
output add_4_pad;
(* src = "examples/my_chip.v:3" *)
output add_5_pad;
(* src = "examples/my_chip.v:5" *)
wire [5:0] b;
(* src = "examples/my_chip.v:2" *)
input b_op_0_pad;
(* src = "examples/my_chip.v:2" *)
input b_op_1_pad;
(* src = "examples/my_chip.v:2" *)
input b_op_2_pad;
(* src = "examples/my_chip.v:2" *)
input b_op_3_pad;
(* src = "examples/my_chip.v:2" *)
input b_op_4_pad;
(* src = "examples/my_chip.v:2" *)
input b_op_5_pad;
(* src = "examples/my_chip.v:5" *)
wire [5:0] sub;
(* src = "examples/my_chip.v:3" *)
output sub_0_pad;
(* src = "examples/my_chip.v:3" *)
output sub_1_pad;
(* src = "examples/my_chip.v:3" *)
output sub_2_pad;
(* src = "examples/my_chip.v:3" *)
output sub_3_pad;
(* src = "examples/my_chip.v:3" *)
output sub_4_pad;
(* src = "examples/my_chip.v:3" *)
output sub_5_pad;
(* module_not_derived = 32'd1 *)
(* src = "examples/my_chip.v:7" *)
simple_adder i_simple_adder (
.a({ a_op_0_pad, a_op_1_pad, a_op_2_pad, a_op_3_pad, a_op_4_pad, a_op_5_pad }),
.b({ b_op_0_pad, b_op_1_pad, b_op_2_pad, b_op_3_pad, b_op_4_pad, b_op_5_pad }),
.c(add)
);
(* module_not_derived = 32'd1 *)
(* src = "examples/my_chip.v:8" *)
simple_sub i_simple_sub (
.a({ a_op_0_pad, a_op_1_pad, a_op_2_pad, a_op_3_pad, a_op_4_pad, a_op_5_pad }),
.b({ b_op_0_pad, b_op_1_pad, b_op_2_pad, b_op_3_pad, b_op_4_pad, b_op_5_pad }),
.c(sub)
);
assign a = { a_op_0_pad, a_op_1_pad, a_op_2_pad, a_op_3_pad, a_op_4_pad, a_op_5_pad };
assign add_0_pad = add[5];
assign add_1_pad = add[4];
assign add_2_pad = add[3];
assign add_3_pad = add[2];
assign add_4_pad = add[1];
assign add_5_pad = add[0];
assign b = { b_op_0_pad, b_op_1_pad, b_op_2_pad, b_op_3_pad, b_op_4_pad, b_op_5_pad };
assign sub_0_pad = sub[5];
assign sub_1_pad = sub[4];
assign sub_2_pad = sub[3];
assign sub_3_pad = sub[2];
assign sub_4_pad = sub[1];
assign sub_5_pad = sub[0];
endmodule
(* cells_not_processed = 1 *)
(* src = "examples/src/simple_adder.v:1" *)
module simple_adder(a, b, c);
(* src = "examples/src/simple_adder.v:2" *)
wire _00_;
(* src = "examples/src/simple_adder.v:2" *)
wire _01_;
(* src = "examples/src/simple_adder.v:2" *)
wire _02_;
(* src = "examples/src/simple_adder.v:2" *)
wire _03_;
(* src = "examples/src/simple_adder.v:2" *)
wire _04_;
(* src = "examples/src/simple_adder.v:2" *)
wire _05_;
(* src = "examples/src/simple_adder.v:2" *)
wire _06_;
(* src = "examples/src/simple_adder.v:2" *)
wire _07_;
(* src = "examples/src/simple_adder.v:2" *)
wire _08_;
(* src = "examples/src/simple_adder.v:2" *)
wire _09_;
(* src = "examples/src/simple_adder.v:2" *)
wire _10_;
(* src = "examples/src/simple_adder.v:2" *)
wire _11_;
(* src = "examples/src/simple_adder.v:3" *)
wire _12_;
(* src = "examples/src/simple_adder.v:3" *)
wire _13_;
(* src = "examples/src/simple_adder.v:3" *)
wire _14_;
(* src = "examples/src/simple_adder.v:3" *)
wire _15_;
(* src = "examples/src/simple_adder.v:3" *)
wire _16_;
(* src = "examples/src/simple_adder.v:3" *)
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire _34_;
wire _35_;
wire _36_;
wire _37_;
(* src = "examples/src/simple_adder.v:4|<techmap.v>:260|<techmap.v>:203" *)
wire [5:0] _38_;
wire [5:0] _39_;
(* src = "examples/src/simple_adder.v:4|<techmap.v>:260" *)
wire [5:0] _40_;
(* src = "examples/src/simple_adder.v:4|<techmap.v>:260|<techmap.v>:221" *)
wire _41_;
(* src = "examples/src/simple_adder.v:4|<techmap.v>:260|<techmap.v>:221" *)
wire _42_;
(* src = "examples/src/simple_adder.v:4|<techmap.v>:260|<techmap.v>:221" *)
wire _43_;
(* src = "examples/src/simple_adder.v:4|<techmap.v>:260|<techmap.v>:222" *)
wire _44_;
(* src = "examples/src/simple_adder.v:4|<techmap.v>:260|<techmap.v>:229" *)
wire _45_;
(* src = "examples/src/simple_adder.v:4|<techmap.v>:260|<techmap.v>:229" *)
wire _46_;
(* src = "examples/src/simple_adder.v:4|<techmap.v>:260|<techmap.v>:221" *)
wire _47_;
(* src = "examples/src/simple_adder.v:2" *)
input [5:0] a;
(* src = "examples/src/simple_adder.v:2" *)
input [5:0] b;
(* src = "examples/src/simple_adder.v:3" *)
output [5:0] c;
NAND2X1 _48_ (
.A(_00_),
.B(_06_),
.Y(_18_)
);
NAND2X1 _49_ (
.A(_01_),
.B(_07_),
.Y(_19_)
);
NOR2X1 _50_ (
.A(_01_),
.B(_07_),
.Y(_20_)
);
XOR2X1 _51_ (
.A(_01_),
.B(_07_),
.Y(_21_)
);
XNOR2X1 _52_ (
.A(_18_),
.B(_21_),
.Y(_13_)
);
OAI21X1 _53_ (
.A(_18_),
.B(_20_),
.C(_19_),
.Y(_22_)
);
AND2X1 _54_ (
.A(_02_),
.B(_08_),
.Y(_23_)
);
NAND2X1 _55_ (
.A(_02_),
.B(_08_),
.Y(_24_)
);
OR2X1 _56_ (
.A(_02_),
.B(_08_),
.Y(_25_)
);
NAND2X1 _57_ (
.A(_24_),
.B(_25_),
.Y(_26_)
);
XNOR2X1 _58_ (
.A(_22_),
.B(_26_),
.Y(_14_)
);
AOI21X1 _59_ (
.A(_22_),
.B(_25_),
.C(_23_),
.Y(_27_)
);
NAND2X1 _60_ (
.A(_03_),
.B(_09_),
.Y(_28_)
);
NOR2X1 _61_ (
.A(_03_),
.B(_09_),
.Y(_29_)
);
XOR2X1 _62_ (
.A(_03_),
.B(_09_),
.Y(_30_)
);
XNOR2X1 _63_ (
.A(_27_),
.B(_30_),
.Y(_15_)
);
OAI21X1 _64_ (
.A(_27_),
.B(_29_),
.C(_28_),
.Y(_31_)
);
AND2X1 _65_ (
.A(_04_),
.B(_10_),
.Y(_32_)
);
NAND2X1 _66_ (
.A(_04_),
.B(_10_),
.Y(_33_)
);
OR2X1 _67_ (
.A(_04_),
.B(_10_),
.Y(_34_)
);
NAND2X1 _68_ (
.A(_33_),
.B(_34_),
.Y(_35_)
);
XNOR2X1 _69_ (
.A(_31_),
.B(_35_),
.Y(_16_)
);
AOI21X1 _70_ (
.A(_31_),
.B(_34_),
.C(_32_),
.Y(_36_)
);
XOR2X1 _71_ (
.A(_05_),
.B(_11_),
.Y(_37_)
);
XNOR2X1 _72_ (
.A(_36_),
.B(_37_),
.Y(_17_)
);
XOR2X1 _73_ (
.A(_00_),
.B(_06_),
.Y(_12_)
);
assign _00_ = a[0];
assign _06_ = b[0];
assign _01_ = a[1];
assign _07_ = b[1];
assign _02_ = a[2];
assign _08_ = b[2];
assign _03_ = a[3];
assign _09_ = b[3];
assign _04_ = a[4];
assign _10_ = b[4];
assign c[1] = _13_;
assign c[2] = _14_;
assign c[3] = _15_;
assign c[4] = _16_;
assign c[5] = _17_;
assign c[0] = _12_;
assign _05_ = a[5];
assign _11_ = b[5];
endmodule
(* cells_not_processed = 1 *)
(* src = "examples/src/simple_sub.v:1" *)
module simple_sub(a, b, c);
(* src = "examples/src/simple_sub.v:2" *)
wire _00_;
(* src = "examples/src/simple_sub.v:2" *)
wire _01_;
(* src = "examples/src/simple_sub.v:2" *)
wire _02_;
(* src = "examples/src/simple_sub.v:2" *)
wire _03_;
(* src = "examples/src/simple_sub.v:2" *)
wire _04_;
(* src = "examples/src/simple_sub.v:2" *)
wire _05_;
(* src = "examples/src/simple_sub.v:2" *)
wire _06_;
(* src = "examples/src/simple_sub.v:2" *)
wire _07_;
(* src = "examples/src/simple_sub.v:2" *)
wire _08_;
(* src = "examples/src/simple_sub.v:2" *)
wire _09_;
(* src = "examples/src/simple_sub.v:2" *)
wire _10_;
(* src = "examples/src/simple_sub.v:2" *)
wire _11_;
(* src = "examples/src/simple_sub.v:3" *)
wire _12_;
(* src = "examples/src/simple_sub.v:3" *)
wire _13_;
(* src = "examples/src/simple_sub.v:3" *)
wire _14_;
(* src = "examples/src/simple_sub.v:3" *)
wire _15_;
(* src = "examples/src/simple_sub.v:3" *)
wire _16_;
(* src = "examples/src/simple_sub.v:3" *)
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire _34_;
wire _35_;
wire _36_;
wire _37_;
wire _38_;
wire _39_;
wire _40_;
wire _41_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:258" *)
wire [5:0] _42_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:260|<techmap.v>:203" *)
wire [5:0] _43_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:260|<techmap.v>:203" *)
wire [5:0] _44_;
wire [5:0] _45_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:260" *)
wire [5:0] _46_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:260|<techmap.v>:221" *)
wire _47_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:260|<techmap.v>:221" *)
wire _48_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:260|<techmap.v>:221" *)
wire _49_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:260|<techmap.v>:222" *)
wire _50_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:260|<techmap.v>:229" *)
wire _51_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:260|<techmap.v>:229" *)
wire _52_;
(* src = "examples/src/simple_sub.v:4|<techmap.v>:260|<techmap.v>:221" *)
wire _53_;
(* src = "examples/src/simple_sub.v:2" *)
input [5:0] a;
(* src = "examples/src/simple_sub.v:2" *)
input [5:0] b;
(* src = "examples/src/simple_sub.v:3" *)
output [5:0] c;
INVX1 _54_ (
.A(_07_),
.Y(_18_)
);
INVX1 _55_ (
.A(_08_),
.Y(_19_)
);
INVX1 _56_ (
.A(_09_),
.Y(_20_)
);
INVX1 _57_ (
.A(_00_),
.Y(_21_)
);
INVX1 _58_ (
.A(_04_),
.Y(_22_)
);
NAND2X1 _59_ (
.A(_06_),
.B(_21_),
.Y(_23_)
);
XOR2X1 _60_ (
.A(_06_),
.B(_00_),
.Y(_12_)
);
AND2X1 _61_ (
.A(_18_),
.B(_01_),
.Y(_24_)
);
XOR2X1 _62_ (
.A(_07_),
.B(_01_),
.Y(_25_)
);
AOI21X1 _63_ (
.A(_06_),
.B(_21_),
.C(_25_),
.Y(_26_)
);
XNOR2X1 _64_ (
.A(_23_),
.B(_25_),
.Y(_13_)
);
NOR2X1 _65_ (
.A(_24_),
.B(_26_),
.Y(_27_)
);
NAND2X1 _66_ (
.A(_19_),
.B(_02_),
.Y(_28_)
);
XOR2X1 _67_ (
.A(_08_),
.B(_02_),
.Y(_29_)
);
INVX1 _68_ (
.A(_29_),
.Y(_30_)
);
OAI21X1 _69_ (
.A(_24_),
.B(_26_),
.C(_30_),
.Y(_31_)
);
NAND2X1 _70_ (
.A(_27_),
.B(_29_),
.Y(_32_)
);
AND2X1 _71_ (
.A(_31_),
.B(_32_),
.Y(_14_)
);
NAND2X1 _72_ (
.A(_28_),
.B(_31_),
.Y(_33_)
);
AND2X1 _73_ (
.A(_20_),
.B(_03_),
.Y(_34_)
);
XOR2X1 _74_ (
.A(_09_),
.B(_03_),
.Y(_35_)
);
AOI21X1 _75_ (
.A(_28_),
.B(_31_),
.C(_35_),
.Y(_36_)
);
XNOR2X1 _76_ (
.A(_33_),
.B(_35_),
.Y(_15_)
);
NOR2X1 _77_ (
.A(_34_),
.B(_36_),
.Y(_37_)
);
XNOR2X1 _78_ (
.A(_10_),
.B(_04_),
.Y(_38_)
);
OAI21X1 _79_ (
.A(_34_),
.B(_36_),
.C(_38_),
.Y(_39_)
);
XNOR2X1 _80_ (
.A(_37_),
.B(_38_),
.Y(_16_)
);
OAI21X1 _81_ (
.A(_10_),
.B(_22_),
.C(_39_),
.Y(_40_)
);
XOR2X1 _82_ (
.A(_11_),
.B(_05_),
.Y(_41_)
);
XNOR2X1 _83_ (
.A(_40_),
.B(_41_),
.Y(_17_)
);
assign _06_ = b[0];
assign _07_ = b[1];
assign _08_ = b[2];
assign _09_ = b[3];
assign _10_ = b[4];
assign _11_ = b[5];
assign _00_ = a[0];
assign _01_ = a[1];
assign _02_ = a[2];
assign _03_ = a[3];
assign _04_ = a[4];
assign _05_ = a[5];
assign c[0] = _12_;
assign c[1] = _13_;
assign c[2] = _14_;
assign c[3] = _15_;
assign c[4] = _16_;
assign c[5] = _17_;
endmodule