Simple framework for physical chip design (place & route) based on KLayout.
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<?xml version="1.0" encoding="utf-8"?>
<klayout-macro>
<description/>
<version/>
<category>pymacros</category>
<prolog/>
<epilog/>
<doc/>
<autorun>false</autorun>
<autorun-early>false</autorun-early>
<shortcut/>
<show-in-menu>false</show-in-menu>
<group-name/>
<menu-path/>
<interpreter>python</interpreter>
<dsl-interpreter-name/>
<text># To be done.
# Layer stack, from bottom (close to transistor) to top.
power_layer_stack = [
(21, 0),
(22, 0)
]
layout = design.layout
top = design.top_cell
l = power_layer_stack[0]
layer = layout.find_layer(*l)
power_cell = layout.create_cell("POWER")
core_area = design.core_area.bbox().to_itype()
width = core_area.width()
height = core_area.height()
pitch_y = 2470
for y in range(core_area.p1.y, core_area.p2.y, pitch_y):
p1 = db.Point(core_area.p1.x, y)
p2 = db.Point(core_area.p2.x, y)
stripe = db.Path([p1, p2], 130)
top.shapes(layer).insert(stripe)
logger.info("Power routing done.")</text>
</klayout-macro>