Simple framework for physical chip design (place & route) based on KLayout.
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<?xml version="1.0" encoding="utf-8"?>
# Path to the gate-level netlist.
netlist_file = get_example_verilog_netlist(file_name='my_chip_45_nl.v')
# Read the netlist.
verilog_reader = VerilogNetlistReader(leaf_circuits=leaf_cells)
netlist = verilog_reader.read_netlist(netlist_file)
# Store the netlist in the design object.
design.netlist = netlist</text>