LibrEDA

The LibrEDA project is focused on creating a libre-software framework for the physical design of silicon chips.

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Rust 0 0

Layout and netlist data structures for the Rust LibrEDA framework.

Updated 7 hours ago

Rust 0 0

Primitive data types and basic routines for Euclidean geometry in the plane. This is developed as a core geometry library of LibrEDA.

Updated 14 hours ago

Layout writer and reader for the OASIS stream format.

Updated 7 days ago

LEF/DEF input and output module for LibrEDA.

Updated 1 week ago

Verilog netlist parser and writer for LibrEDA. Only supports the structural Verilog syntax as used by Yosys.

Updated 1 week ago

Example router implementation for the LibrEDA framework.

Updated 2 weeks ago

Repository holding the cargo workspace of LibrEDA with all sub-projects. This is meant as a way to distribute the most recent source-code.

Updated 2 weeks ago

Boolean operations on polygons for the `iron-shapes` crate.

Updated 2 weeks ago

Standard-cell legalizer example implementations for the LibrEDA place&route framework.

Updated 2 weeks ago

Rust 0 0

ASIC place & route framework. This crate contains interface definitions of the core parts of the place & route flow.

Updated 2 weeks ago

A minimal place & route flow build on top of the LibrEDA framework and the FreePDK45. This is work-in-progress but already good enough for a demonstration.

Updated 2 weeks ago

Example standard-cell placement engine for the LibrEDA-Rust framework. This placement algorithm simulates the movement of electric charges that are sparsely connected by springs (wires).

Updated 2 weeks ago

HTML 0 0

LibrEDA project web page.

Updated 4 weeks ago

Python 0 0

Simple framework for physical chip design (place & route) based on KLayout.

Updated 2 months ago

Example clock-tree generator for the LibrEDA framework

Updated 4 months ago

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