LibrEDA

The LibrEDA project is focused on creating a libre-software framework for the physical design of silicon chips.

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Example clock-tree generator for the LibrEDA framework

Updated 3 days ago

liberty-io
Rust 0 0

Rust crate of a parser and writer for the 'liberty' format which is used to describe the timing behavior of CMOS standard-cells.

Updated 3 days ago

pages
HTML 0 0

LibrEDA project web page.

Updated 3 days ago

Example router implementation for the LibrEDA framework.

Updated 4 days ago

iron-shapes
Rust 0 0

Primitive data types and basic routines for Euclidean geometry in the plane. This is developed as a core geometry library of LibrEDA.

Updated 6 days ago

LEF/DEF input and output module for LibrEDA.

Updated 1 week ago

libreda-pnr
Rust 0 0

ASIC place & route framework. This crate contains interface definitions of the core parts of the place & route flow.

Updated 1 week ago

Layout writer and reader for the OASIS stream format.

Updated 1 week ago

libreda-db
Rust 0 0

Layout and netlist data structures for the Rust LibrEDA framework.

Updated 1 week ago

Boolean operations on polygons for the `iron-shapes` crate.

Updated 1 week ago

Standard-cell legalizer example implementations for the LibrEDA place&route framework.

Updated 1 month ago

splay
Rust 0 0

Splay map and splay set data structures.

Updated 1 month ago

Verilog netlist parser and writer for LibrEDA. Only supports the structural Verilog syntax as used by Yosys.

Updated 1 month ago

Netlist reader and writer implementations for the JSON format used by Yosys.

Updated 1 month ago

LibrEDA
SVG 1 0

Libre EDA Project. LibrEDA aims to create a libre software framework for the physical design of silicon chips. This repository is a project management repository. It is used to keep track of general milestones etc.

Updated 2 months ago

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