The LibrEDA project is focused on creating a libre-software framework for the physical design of silicon chips. Hint: use the libreda-rs-workspace repo for development.

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LibrEDA project web page.

Updated 2023-09-15 07:36:09 +00:00

Core traits and data types for representation and manipulation of logic functions.

Updated 2023-08-17 13:01:14 +00:00

Parallel graph processing using an operator formulation.

Updated 2023-08-16 13:27:17 +00:00

Fast lookup-table based computation of rectilinear Steiner minimal trees (RSMT).

Updated 2023-08-16 11:19:58 +00:00

Repository holding the cargo workspace of LibrEDA with all sub-projects. This is meant as a way to distribute the most recent source-code.

Updated 2023-08-16 11:19:00 +00:00

Boolean operations on polygons for the `iron-shapes` crate.

Updated 2023-08-16 11:18:27 +00:00

The ultimate guide through LibrEDA.

Updated 2023-08-16 11:17:46 +00:00

Layout and netlist data structures for the Rust LibrEDA framework.

Updated 2023-08-16 11:17:21 +00:00

Simple library for parsing data from iterators.

Updated 2023-08-16 11:15:59 +00:00

Splay map and splay set data structures.

Updated 2023-08-16 11:15:32 +00:00

Primitive data types and basic routines for Euclidean geometry in the plane. This is developed as a core geometry library of LibrEDA.

Updated 2023-08-16 11:14:57 +00:00

Interpolation of one and two dimensional arrays.

Updated 2023-08-16 11:13:53 +00:00

Rust crate of a parser and writer for the 'liberty' format which is used to describe the timing behavior of CMOS standard-cells.

Updated 2023-07-16 09:34:09 +00:00

Static timing analysis (STA) for netlists of the LibrEDA framework.

Updated 2023-07-14 13:57:12 +00:00

Verilog netlist parser and writer for LibrEDA. Only supports the structural Verilog syntax as used by Yosys.

Updated 2023-07-14 11:48:10 +00:00

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