A PCIe interface for the ECP5 FPGA written in nMigen
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ECP5-PCIe fed0b91ab9 Add onboard refclk in case host doesn't provide a refclk 3 months ago
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avr_test.py change to amaranth 5 months ago
generate_lfsr.py (de)scrambling working, LTSSM gets to L0 2 years ago
lfsr_states.csv (de)scrambling working, LTSSM gets to L0 2 years ago
oscg_test.py change to amaranth 5 months ago
pcie_adapter.py change to amaranth 5 months ago
pll_test.py change to amaranth 5 months ago
rp64_pcie_init.py change to amaranth 5 months ago
sim_crc_x2.py change to amaranth 5 months ago
sim_crc_x4.py change to amaranth 5 months ago
sim_dllp_rx.py change to amaranth 5 months ago
sim_dllp_tx.py change to amaranth 5 months ago
sim_lfsr.py change to amaranth 5 months ago
sim_rx.py change to amaranth 5 months ago
sim_tx.py change to amaranth 5 months ago
sim_tx_rx.py change to amaranth 5 months ago
test_config_mem.py Add configuration memory 5 months ago
test_crc.py change to amaranth 5 months ago
test_memory.py change to amaranth 5 months ago
test_pcie_1.py change to amaranth 5 months ago
test_pcie_ltssm.py Add onboard refclk in case host doesn't provide a refclk 3 months ago
test_pcie_phy.old.py change to amaranth 5 months ago
test_pcie_phy.py Add onboard refclk in case host doesn't provide a refclk 3 months ago
test_pcie_serdes_x1.py change to amaranth 5 months ago
test_pcie_serdes_x2.py change to amaranth 5 months ago
test_pcie_serdes_x4.py change to amaranth 5 months ago
test_pcie_virtual.py Disable RX equalizer and a few other bugfixes 5 months ago
test_phi_ber.py change to amaranth 5 months ago
test_rx_tx_discrepancy.py change to amaranth 5 months ago
test_serdes_x2_speed.py change to amaranth 5 months ago
upload.sh upload gateware and rx/tx phase testing 2 years ago