A PCIe interface for the ECP5 FPGA written in nMigen
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ECP5-PCIe 41b135388c PLL testing 2 years ago
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.vscode PLL testing 2 years ago
avrdude_basic.cpp ATMega programmer and basic code for it, 16 MHz clock generator and UART passthrough, PLL diff pairs added 2 years ago
compile.py PLL testing 2 years ago
pll_test.cpp PLL testing 2 years ago